Stream Processing
 
 
As microprocessor architectures advance performance through the incorporation of large numbers of cores, developers of high-performance applications face new challenges in designing efficient algorithms to take advantage of these complex architectures.

Today's High Performance Computing (HPC) and Real-time Embedded Systems are also turning to powerful but exotic devices such as FPGAs, Cell Processors, Graphics Processing Units and others to accelerate critical computational tasks. While these devices offer the opportunity for extraordinary performance gains, their unique architectures create new programming challenges. These problems become amplified as HPC manufactures build systems with heterogeneous processing elements for accelerating specialized computing tasks.

The common element tying together these different programming challenges is the need to express concurrent operations and their interactions efficiently. Pentum Group has developed the tools StreamSC and StreamVSIPL to address this broad collection of programming challenges.

StreamSC
StreamSC is a basic toolbox to express data flows based on a stream processing paradigm. StreamSC is based on the ideas of SystemC, system simulation language that provides an efficient framework for hardware systems designers to simulate their hardware designs for correctness and efficiency.

With StreamSC, the developer expresses application function as a graph of flows from one work center to another workcenter. An example of this kind of algorithmic data flow is shown in the diagram above. By capturing the abstract geometry of workflow, automatic tools can efficiently map expressed workflow to the physical resources of the target platforms and devices.

StreamSC is designed to result in high performance with traditional shared memory microprocessors, exotic streaming devices such as FPGAs or cell processors., as well as with highly parallel systems with hundreds and thousands of processors.

StreamSC formally separates the concerns of communication and computation with a pipeline operation and stream model. Streams are responsible for memory management and communication, while pipeline operations perform specific tasks.

StreamSC employs an asynchronous model for streams to interact with pipeline operations. The application programmer merely specifies pipeline operation placement, and the underlying machinery of streams and ensures efficient communication between differing pipeline operation centers and no matter where they are. The StreamSC communication semantics eliminate many of the traditional race condition problems that plague current methods of parallel programming.

The objects of StreamSC can have complex structures such as vectors matrices or tensors.

StreamSC is available in both a C++ and SystemC API. StreamSC provides a simple and intuitive programming interface to express complex workflow.

StreamVSIPL
StreamVSIPL complements StreamSC with a library of stream oriented scientific subroutines that can be easily linked together through StreamSC to produce complex powerful and high-performing applications. StreamVSIPL is based on the VSIPL family of scientific subroutine libraries developed by the Department of Defense to encourage standards-based applications for deployed weapons systems.

The goal of StreamVSIPL is to provide open standards-based tunable task targets suitable for a wide variety of processing architectures. Open standards promote portability, reduce the cost of upgrades, and helps to drive down overall system development costs.

Please contact us to see if StreamSC and SystemVSIPL are right for your next project.

Site designed by: Liquis Web Design